Solid state storage devices use analog memory cells to store data. Each memory cell stores a storage value, such as an electrical voltage. The storage value represents the information stored in the memory cell. Many solid state storage devices distinguish between different binary values that a memory cell may store based on a read voltage level of the memory cell. The range of possible storage values for each memory cell is typically divided into threshold regions, with each region separated by a read threshold voltage and corresponding to one or more data bit values. Ideally, all of the memory cells in a given solid state storage device have identical read threshold voltages for the logical bit values stored. In practice, however, the read threshold voltages differ across the cells in probability distributions along the read threshold voltage axis (e.g., “read threshold voltage distributions”) that are similar to a Gaussian distribution.
In addition, solid state storage devices can shift over time. For example, memory cell leakage, memory cell damage and other disturbances to memory cells can alter the read voltage levels of the memory cells. Thus, the read threshold voltages can shift over time. The rate of leakage and other disturbances can also increase with age as memory cells are used over time. If the read voltage level of a memory cell shifts past a read threshold voltage, a data error occurs, as the value of the data read from the memory cell is different than the value of the data that was written to the memory cell.
Data is read from a non-volatile memory in blocks referred to herein as a “read unit” or as a “codeword” that is typically protected from error by included error correction, such as included parity bits generated using an error correction algorithm, such as low density parity check (LDPC) encoding. Under control of a solid state disk controller, bits are read from non-volatile memory cells. The resulting data is decoded to apply the error correction algorithm, for example, in LDPC decoder. If the data fails to converge in the LDPC decoder, a read retry operation can be used to re-read the data and to again apply the error correction algorithm. Although cell voltage is continuous, non-volatile memory cells generally provide only binary hard decisions after a read operation. When soft iterative decoding algorithms, such as LDPC decoding algorithms, are used for error correction, it is desirable to convert the hard decisions generated by the non-volatile memory into soft decisions that give the decoder more information to help correct errors. The soft decisions converted from a single read may not be of sufficient quality for successful decoding. In this case, multiple reads with varying read voltages can be used to obtain sufficient quality of the soft decisions. Thus, the location and frequency of the read reference voltages can directly affect the quality of the soft decision and eventually, the theoretic information content of the channel reads.
A need remains for improved techniques for performing read retry operations.